SDRAM integrated circuit devices are well known in the art. One embodiment showing major subcircuits in the write path 10 of an SDRAM are shown in FIG. 1. Shown are various relevant bond pads 12 for the SDRAM that allow the SDRAM to be coupled to an outside system via the integrated circuit's packaging (not shown). These bond pads 12 include various signals sent from the outside system (such as a microprocessor), and include: a system clock (Clk); various command signals such as Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE), and Chip Select (CS); address lines (Ax) for specifying an address in the memory array (not shown) to which data is to be written; data lines (DQx) for providing to the to-be-written data; and a Write Strobe (WS) for toggling the data into the SDRAM. Generally, the write path can be thought of as comprised of two main sections: the data path 6 and the command path 8. As one skilled in the art will recognize, a typical SDRAM will have many more address and data lines than those shown.
The illustrated SDRAM is a Double Data Rate (DDR) SDRAM, meaning that data is latched into the SDRAM (via latches 18a-18c) on both rising and falling edges of the intermittently-asserted Write Strobe. Moreover, as illustrated, the SDRAM has a burst length of four, meaning that four bits are written into each data line per each write command. As a result, notice that the latches 18a-18c are coupled to deserializers 20a-20c. These deserializers 20a-20c serially receive the four burst bits of data from the latches 18a-c and, under control of a deserializer control 22, provide the four bits of data in parallel along busses 23a-23c. With the data deserialized, the data on the buses 23a-23c can be written to the memory array (not shown) at a specified address. While a burst length of four is illustrated for convenience, one skilled will realize that other burst lengths are possible, and can be programmed into the SDRAM. Moreover, one skilled will further realize that while illustrated in the context of a DDR SDRAM for simplicity, the same operational principles apply to DDR2 (i.e., four bits per WS rising/falling edge) and DDR3 (i.e., eight bits per WS rising/falling edge) SDRAM technologies.
Data is written to the illustrated SDRAM through the issuance of a write command, which in turn requires assessment of the various command signals (e.g., RAS, CAS, WE, CS) issued external to the device. For example, in a typical SDRAM, a write command corresponds to /CS=‘0’, /RAS=‘1’, /CAS=‘0’, and /WE=‘0’, although this can differ between various devices. In any event, for the SDRAM to understand that data is to be written at a particular point in time, the command signals must be decoded via command decode 24, which in turn issues an Internal Write command when the conditions for writing have been properly presented to the device.
As is typical of DDR2 SDRAMs, the illustrated SDRAM in FIG. 1 has a write latency. As is known, a write latency is a number of cycles of the system clock (Clk) between the presentation at the pads 12 of a write command and the presentation at the pads 12 of the data corresponding to that write command. The write latency is generally variable as a function of the frequency of the system clock, and can be programmable, but assume for simplicity in the illustrated SDRAM that the write latency is four cycles. If this is the case, the Internal Write command signal is held in check for four cycles by a write latency counter 26, which functions to delay the assertion of the Internal Write command as a Write Valid command on line 28 until the write latency counter has counted four clock cycles.
Once the Write Valid command has been asserted in this fashion, it is presented to the deserializer control 22, which also receives both the system clock (Clk) on line 27. When the Write Valid signal coincides with the rising edge of the system clock, deserializer control 22 enables the deserializers 20 to output the deserialized data in parallel onto the buses 23a. At that point, and in theory, the data on the buses 23 is written into the array at the address earlier presented to the device.
This basic scheme and circuitry for the write path 10 of a SDRAM as shown in FIG. 1 is not optimal, particularly at high system clock frequencies. Specifically, a problem results from a potential lack of synchronization between the data path 6 and the command path 8, and more specifically from a lack of synchronization between the Write Valid signal and the Write Strobe. Without proper Write Valid to Write Strobe alignment, it is possible that the deserializer control 22 will enable the data drivers in the deserializers 20 to drive data on the parallel bus 23 misaligned to the incoming data from the data capture latches 18 and the deserializer circuits 20, with the result that incorrect data may be presented at the parallel buses 23. A particular problem is presented when the delay in presentation of the Write Valid signal to the deserializer control 22 is on the order of the system clock period.
However, while it is important to align the Write Valid signal with the Write Strobe signal, this is difficult to accomplish in a typical SDRAM. One reason it is hard to align these two signals is that the Write Valid signal is ultimately generated from the system clock (Clk), which itself may not be aligned to the Write Strobe despite best efforts by the external system to do so. In fact, such synchronization between the system clock and the Write Strobe is not easily attained, because unlike the system clock in the command path 8, the Write Strobe in the data path 6 is not a continually-running clock. Instead, the Write Strobe is issued by the external system only intermittently in burst form during a write.
Another reason that it is hard to align these two signals is that the Write Valid signal must travel a very long distance along the device from its point of assertion (i.e., from write latency command 26) to its point of receipt (i.e., at the deserializer control 22). This is because the system clock (Clk), command latches (18d), command decode 24 and write latency counter 26, generally are laid out at a central location on the device, while the data input latches (18a-c), deserializers (20a-c), and deserializer control 22 are generally laid out at peripheral locations. As a result, timing the arrival of the Write Valid signal at the deserializer control 22 can and will vary appreciably due to process variations, whereas the arrival of the Write Strobe signal, which travels only a relatively short distance to the deserializer control 22, will be more predictable and less variant.
(It should be noted in passing that the system clock, Clk, too must travel essentially the same long distance along line 27 than does the Write Valid signal on line 28. However, to ensure proper timing between these two signals at the deserializer, extra delay (not shown) is typically added to the Write Valid signal line 28 to ensure that it arrives at the deserializer control 22 correctly aligned to the distributed system clock 27. Because these signals travel along essentially the same path, they are equally affected by processing variations, and hence are always generally synchronized at the deserializer control 22).
Previous solutions to this write latency tracking synchronization problem have involved the use of delays to match the write decode path with the data path. However, such routing delays can become much greater than the period of the system clock. This can lead to timing errors for write latency estimation, particularly when process, voltage, and temperature gradients across the SDRAM are considered.